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SP8401
Very Low Phase Noise 300MHz / 10/11
DS3230
ISSUE 3.1
April 1994
The SP8401 is a very low phase noise variable modulus divider. Special circuit techniques have been used to reduce the phase noise considerably below that produced by standard dividers. The modulus control input is CMOS or TTL compatible. The SP8401 is packaged in a 28 pin plastic SO package to be compatible with the SP8400 and SP8402 devices.
Ordering Information
SP8401 KG MPES(Commercial Grade)
FEATURES
I Very low Phase Noise (Typically -160dBc/Hz at 1kHz offset) I Supply Voltage 5V
N/C N/C N/C VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V N/C MODULUS CONTROL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 N/C N/C N/C N/C N/C N/C N/C OUTPUT OUTPUT N/C VCC +5V N/C N/C N/C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Output Current Storage Temperature Range Maximum Clock Input Voltage 6.5V 20mA -55C to +125C 2.5V p-p
MP28
Fig.1 Pin connections - top view
0 -10 -20 -30 -40 -50
(f) (dBc/Hz) -3dB
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 1 10 100 Frequency (Hz) 1k 10k 100k
Fig.2 Typical single sideband phase noise measured at 300MHz
SP8401
ELECTRICAL CHARACTERISTICS
Guaranteed over: Supply voltage V CC = +4.75V to +5.25V Temperature Tamb = -10C to +75C Tested at +4.75V and +5.25V at T amb = +25C Characteristic Supply current Output voltage swing Input sensitivity 50MHz to 300MHz Pin Min. 4, 11, 12, 18 20, 21 7, 8 50 340 Value Typ. Max. 57 440 64 mA mV mV dBm Output loaded with 300R See Fig.5 p-p @ 330MHz input / 11 mode Output loaded with 300R RMS Sine wave into 50 Ohms (dBm equivalent) See Fig.3 Units Conditions
140 (-4)
Modulus Control Inputs Logic high voltage Low low voltage Input current Set up time ts Release time tr
14 14 14 14 14
2.2 0.8 180 4 4
V A ns ns
/ 10 mode / 11 mode Modulus control input voltage 5V
400 355mV VIN mV RMS 300 OPERATING WINDOW 200 140mV 100
0
50
100
150
200
250
300
350
INPUT FREQUENCY (MHz)
Fig.3 Typical input sensitivity
CLOCK INPUT MODULUS CONTROL INPUT tr 6 OUTPUT 5 5 ts
Fig.4 Timing diagram
2
SP8401
VCC
1 2 3 4 5
28 27 26 25 24 23 22
1nF 50R RF SIGNAL GENERATOR
6 7 8 9 10 11 12 13
SP8401
21 20 19 18 17 16 15
220nF OUTPUT
TTL/CMOS MODULUS CONTROL
14
50R 1nF 10nF 1nF 2x330R 10nF
Fig.4 Test circuit
3
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